The carrier mobility in a MOS transistor has a significant impact on power consumption and switching performance of the device. Improvement in carrier mobility allows faster switching speed and allows for operation at low voltages, resulting in reduced power consumption.
Mechanical stress engineering has been employed in MOS transistors to improve carrier mobility. Tensile stress on a channel region causes increased current in an NMOS transistor but causes decreased current in a PMOS transistor. Compressive stress on the channel region causes increased current in a PMOS transistor but causes decreased current in an NMOS transistor.
FIG. 1 is a schematic cross-sectional view of a MOS device illustrating an approach to introducing mechanical stress to improve carrier mobility in the device. The device is formed in a substrate 10 and is isolated by isolation regions 12 formed in the substrate 10. The transistor device includes source/drain regions 22, 26 formed in the substrate 10 defining a channel region 18 therebetween. A gate structure includes a gate dielectric 14 formed on the substrate 10, a conductive gate layer 20 over the gate dielectric and a silicide layer 30 formed over the conductive gate layer 2Q. Insulating sidewall spacers 24 are formed on the sidewalls of the gate structure.
Mechanical stress is introduced into the channel 18 by a stress control layer 40 formed over the gate structure and the top surface of the source/drain regions 26 and substrate 10. Specifically, tensile stress is introduced into the MOS transistor structure as indicated by the arrows in the figure. Another approach to introducing tensile stress into the channel 18, as illustrated by the arrows in FIG. 1, is the silicide layer 30 formed in the source/drain regions 22, 26. After silicidation, the silicide regions 30 occupy less volume than the original source/drain material replaced by the silicide. As a result, tensile stress is introduced into the channel 18.
In addition to the improvement in carrier mobility, the introduction of mechanical stress into a MOS transistor has also been shown to degrade the performance of the device by introducing electrical noise, specifically, flicker noise. Flicker noise, also commonly referred to as “1/f noise,” is a type of noise whose power spectrum P(f) as a function of frequency f behaves in accordance with P(f)=1/fa, where a is very close to 1. Flicker noise is also commonly referred to as “pink noise” because most of the noise power is concentrated at the lower end of the frequency spectrum. Flicker noise is considered to be caused not only by the trapping and detrapping of carriers, but also by mobility modulation via carrier scattering due to the trapped charges. Flicker noise degradation can be an important factor for both low frequency analog circuits and high performance digital circuits. Although the flicker noise is generated at relatively low frequencies, the noise may be very significant to some RF circuits since it is up-converted to the high frequency spectrum and degrades the coherency of oscillation.
FIGS. 2A and 2B are graphs illustrating the relationship between stress engineering in a MOS device and noise. FIG. 2A is a graph of the noise power Svg distribution between stress-enhanced and stress-attenuated transistors. The measurements are taken at Vd=0.05V and V g=0.85V for an NMOS device, and Vd=−0.05V and Vg=−0.85V for a PMOS device. FIG. 2B is a graph of Noise Power Ratio versus maximum transconductance (Gmmax) improvement ratio of a CMOS device. The graph of FIG. 2B illustrates that both tensile and compressive stress on a MOS device degrade performance from the standpoint of flicker noise.
Hence, enhanced stress engineering applied to MOS devices improves performance of MOS transistors but degrades flicker noise characteristics. That is, in both NMOS and PMOS devices, both tensile stress and compressive stress enhance performance of the devices but degrade the flicker noise characteristics of both devices. Therefore, stress engineering is not always an acceptable means for improving overall circuit performance, when flicker noise characteristics are considered, such as, in particular, in analog applications, RF applications and mixed-signal applications, e.g., system LSI applications.